1. Field of the Invention
The present invention relates to a power line layout and, more particularly, to a power line layout that may provide a reduction of noise and an increase in power supply efficiency in a semiconductor device.
2. Description of the Related Art
In general, a semiconductor device may include a plurality of memory cells arranged at predetermined intervals in a grid structure. A bit line sense amplifier may be disposed at a first side of each of the memory cell regions, and a sub wordline driver may be disposed at a second side of each of the memory cell regions, for example. A region in which the bit line sense amplifier is disposed may be referred to as a sense amplifier region, and a region in which a sub wordline driver is disposed may be referred to as a sub wordline driver region.
Typically, a semiconductor device may receive power through horizontally or vertically arranged power lines. The power lines may be utilized to drive memory cell regions and bit line sense amplifiers. Conventional power lines may be divided into a plurality of first power lines vertically arranged in the sense amplifier region and a plurality of second power lines horizontally arranged in the memory cell region and the sub wordline driver region. The first power lines may be located at a position lower than the second power lines in the semiconductor device. In other words, in the semiconductor device, the power lines may be arranged in a two-layer structure.
Various voltages may be supplied to the semiconductor device through the power lines. The number of voltages supplied through the power lines may vary. For example, the number of voltages supplied through the power lines may be determined based at least, in part, on how many voltages the semiconductor device may utilize for operation.
Furthermore, the number of power lines employed in a semiconductor device may be determined based at least, in part, on characteristics of the semiconductor device. As a few examples, the number of first and second power lines to be employed in a semiconductor memory device may depend at least, in part, on the capacity of the semiconductor memory device, a wordline enable signal line pitch of the semiconductor memory device and/or wordline enable signal line width of the semiconductor memory device.
The first power lines may be vertically arranged in the sense amplifier region, and the second power lines may be horizontally arranged in the sub wordline driver region. The first and second power lines may be connected using via contacts in a mesh structure in a manner such that the connected first and second power lines have the same voltage levels. For example, power lines of the first power lines receiving a high voltage may be connected to power lines of the second power lines receiving a high voltage through via contacts. In a conventional power line layout, power supplied through the second power may be utilized as main power.
Wordline enable signal lines may be vertically arranged in the memory cell region. The wordline enable signal lines may be arranged in the same layer as the first power lines or the second power lines. In operation, noise may be generated in the power lines. Increasing the number of via contacts may distribute noise, but the layout of the semiconductor device may limit the ability to increase the number of via contacts. Additionally, reducing the power may decrease the generation of noise, but may additionally decrease the operating speed of a semiconductor device. A need, therefore, exists for a power line layout that addresses one or more of these limitations of the conventional art.